A ferroelectric random access memory (FeRAM) generally includes an array of FeRAM cells where each FeRAM cell contains at least one ferroelectric capacitor. Each ferroelectric capacitor contains a ferroelectric material sandwiched between conductive plates. To store a data bit in a FeRAM cell, a write operation applies write voltages to the plates of the ferroelectric capacitor in the FeRAM cell to polarize the ferroelectric material in a direction associated with the data bit being written. A persistent polarization remains in the ferroelectric material after the write voltages are removed and thus provides non-volatile storage of the stored data bit.
A conventional read operation for a FeRAM determines the data bit stored in a FeRAM cell by connecting one plate of a ferroelectric capacitor to a bit line and raising the other plate to a read voltage. If the persistent polarization in the ferroelectric capacitor is in a direction corresponding to the read voltage, the read voltage causes a relatively small current through the ferroelectric capacitor, resulting in a small charge and voltage change on the bit line. If the persistent polarization initially opposes the read voltage, the read voltage flips the direction of the persistent polarization, discharging the plates and resulting in a relatively large charge and voltage increase on the bit line. A sense amplifier can determine the stored value from the resulting bit line current or voltage.
Development, manufacture, and use of an integrated circuit such as FeRAM often require testing that determines the characteristics of the integrated circuit and determines whether the integrated circuit is functioning properly. One important test for a FeRAM is measurement of the charge delivered to bit lines when reading memory cells. Generally, the bit line charge or voltage that results from reading a FeRAM cell varies not only according to the value stored in the FeRAM cell but also according to the performance of the particular FeRAM cell being read. The distribution of delivered charge can be critical to identifying defective FeRAM cells that do not provide the proper charge and to selecting operating parameters that eliminate or minimize errors when reading or writing data.
A charge distribution measurement generally tests each FeRAM cell and must measure the amount of charge read out of the FeRAM cell for each data value. Measuring the readout charge commonly requires using a sense amplifier to compare a bit line signal read from the FeRAM cell to up to 100 or more different reference levels. Each of the comparisons generates a binary signal indicating the result of the comparison. The binary comparison result signals can be output using the same data path used for read operations. Comparing the bit line voltage read from a single FeRAM cell storing a data value xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d to 100 reference voltages generates 100 bits of test data. Accordingly, the amount of test data generated during a distribution measurement for all cells in an FeRAM requires a relatively long time to output using the normal I/O cycle time. Charge distribution measurement for data values xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d in a 4-Megabit FeRAM, for example, can generate more than 8xc3x97108 bits of test data, which may require several minutes to output. Further, the amount of test data and output time increase with memory storage capacity.
The large volume of data output from a FeRAM for a charge distribution measurement may require too much time for an efficient testing during integrated circuit manufacture. Processing the large amount of data to construct bit line voltage distributions can also create a bottleneck in a fabrication process. Testing only a sampling of the FeRAM cells in a FeRAM can reduced the amount of data, but sampling may fail to uncover some defective FeRAM cells.
In view of the current limitation of methods for measuring charge distributions of FeRAMs, structures and methods that reduce the data flow and processing burdens for measurement of charge distributions are sought.
In accordance with an aspect of the invention, an on-chip circuit measures the distribution of bit line voltages or charges resulting from reading memory cells such as FeRAM cells and compresses distribution or bit line voltage data. The measurement of a bit line voltage or charge typically involves operating a sense amplifier to compare a bit line signal to a series of reference signals. Instead of directly outputting result signals from the sense amplifier, a compression circuit processes the result signals to reduce the amount of data but retain the information important to bit line voltage or charge distribution measurement. The compression can also convert bit line voltage measurements and the charge distribution data into forms that are easier to use in the memory or during external processing.
One embodiment of a compression circuit includes a counter and a set of registers or other storage elements connected to the counter. The counter is synchronized with changes in a reference signal input to sense amplifiers and to the series of comparisons so that the count from the counter indicates a current reference voltage that sense amplifiers are comparing to respective bit line voltages. Each storage element corresponds to a bit line being tested and operates to store the count from the counter when the binary result values from a corresponding sense amplifier has a particular value or changes from one value to another. The stored value at the end of the bit line voltage measurement is a count value indicating the reference voltage (or count) that the comparisons first or last indicated as greater than the bit line voltage. To quantify noise in the comparisons, multiple count values for each bit line can be stored using different triggering conditions so that the count values indicate when more than one transition occurs in the results stream.
One specific embodiment of the invention is a method for testing an integrated circuit containing memory cells such as FeRAM cells. The method starts with reading out a signal from one of the memory cells to a bit line, biasing a reference line to a first/next voltage from a series of reference voltages, and generating a result signal indicating whether the first/next voltage on the reference line is higher than a voltage on the bit line. These steps can be repeated for each of the series of reference voltages, although repeated reading out of the signal from a memory cell is not required if the sense amplifier used in generating the result signal does not disturb the bit line signal. The repeated steps generate a series of values of the result signal, and the series of values can be compressed using on-chip circuitry to generate a compressed measurement value.
One way to compress the series of result signals includes: changing an index value each time the reference line is biased to the first next voltage from the series of voltages; applying the result signal to a storage element having the index value as an input data value; and storing the index value in the memory when the value of the result signal satisfies a condition that enables the memory. After the series of comparisons, the stored value in the memory is the compressed measurement result. To reduce the amount of data output for a bit line voltage distribution measurement, the compressed measurement value can be output from the FeRAM without outputting the series of values of the result signal. The compressed measurement value can also be used in the FeRAM, for example, by an adjustment circuit that sets parameters according to a bit line voltage distribution.
Another embodiment of the invention is an integrated circuit including an array of FeRAM cells, a reference voltage generator, sense amplifiers, and an on-chip compression circuit. The reference voltage generator operates in a test mode to generate a reference signal that sequentially has a series of voltages. The sense amplifiers, which have inputs connected to the bit lines and the reference voltage generator, generate a result signal representing values that the compression circuit compresses. The on-chip compression circuit can compress a series of result values from one of the sense amplifiers to generate a compressed value that typically indicates a location in the series of result values at which the result values transition from one level to another level.
One embodiment of the compression circuit includes a counter and a set of storage elements. The counter changes a count/index value to correspond to a reference voltage that the reference voltage generator supplies to the sense amplifiers. Each storage element is coupled to receive the count/index value and a result signal indicating a result of a sensing operation during which a corresponding one of the sense amplifiers compares a bit line voltage to the reference signal. In response to the result signal having a first value, the storage element sets a stored value equal to the count/index value, and in response to the result signal having a second value, the storage element leaves the stored value unchanged. The stored value at the end of the series of values of the result signal is a compressed measurement value, which can be output from the FeRAM or used internally in the FeRAM.